[VHDL]エッジ待ちシミュレーション

パッケージの練習を兼ねてVHDLで気軽にエッジ待ちシミュレーション出来るようなパッケージを作成
[Verilog]repeat(10) @(posedge CLK);
[VHDL ]wait_posedge(CLK, 10);

【環境】
・Modelsim10.5b(Intel FPGA Starter Edition)

【参考】
・シミュレーション用パッケージ

-- sim_pack.vhd
---------------------------------------------------
-- Package                                       --
-- シミュレーション用タスクパッケージ            --
--  1.Wait立上りエッジ                           --
--  2.Wait立下りエッジ                           --
---------------------------------------------------
library  IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

-- Package Header ---------------------------------
package sim_pack is
--  1.Wait立上りエッジ                           --
  procedure wait_posedge(
    signal SIG   : in  std_logic;
           CYCLE : in  integer  :=1
  );
--  2.Wait立下りエッジ                           --
  procedure wait_negedge(
    signal SIG   : in  std_logic;
           CYCLE : in  integer
  );
end sim_pack;

-- Package Body -----------------------------------
package body sim_pack is

  procedure wait_posedge(
    signal SIG   : in std_logic;
           CYCLE : in integer  :=1
  ) is
  begin
    for w in 1 to CYCLE loop
      wait until SIG'event and SIG = '1';
    end loop;
  end wait_posedge;


  procedure wait_negedge(
    signal SIG   : in std_logic;
           CYCLE : in integer
  ) is
  begin
    for w in 1 to CYCLE loop
      wait until SIG'event and SIG = '0';
    end loop;
  end wait_negedge;

end sim_pack;

・テストベンチサンプル

-- TestBench.vhd
library  IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- Debug --
use IEEE.std_logic_textio.all;
library STD;
use STD.textio.all;
library  work;
use work.sim_pack.all;

entity TB is 
end TB;

architecture testbench of TB is
  -- Signal -----------
  constant   CYCLE   : Time    := 100 ns;
  signal     CLK     : std_logic;
  signal     RST_N   : std_logic;
  signal     finish  : boolean :=false;
begin
  -- Clock Generator --
  Clock : process begin
    CLK <= '0';
    wait for (CYCLE/2);
    CLK <= '1';
    wait for (CYCLE/2);
    if(finish) then wait; end if;
  end process;
  
  -- Senario ----------
  Main : process
    variable   lout    : line;
  begin
    RST_N <= '0';
    wait_posedge(CLK,  10); --  10 cycle wait
    RST_N <= '1';
    wait_posedge(CLK, 100); -- 100 cycle wait
    finish <= true; -- Sim finish nitify Other process
    wait;
  end process;
  
  Sub  : process
    variable   lout    : line;
    variable   cnt     : integer := 0;
  begin
    wait_posedge(RST_N, 1); -- Reset release
    while finish=false loop
      wait_posedge(CLK, 1); -- 1 cycle wait
      cnt := cnt + 1;
      write(lout, "wait " & to_string(cnt) & "Cycle.");
      writeline(output, lout);
    end loop;
    write(lout, string'("Simuration Finish."));
    writeline(output, lout);
    wait;
  end process;

end testbench;

【実行】
$vcom -work work -2008 sim_pack.vhd TestBench.vhd
$vsim work.TB -do "run -all; quit"